35 lines
542 B
Verilog
35 lines
542 B
Verilog
// Check that nested real typed class properties can be used as lvalues.
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module test;
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bit failed = 1'b0;
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`define check(val, exp) do \
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if (val != exp) begin \
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$display("FAILED(%0d). '%s' expected %f, got %f", `__LINE__, `"val`", exp, val); \
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failed = 1'b1; \
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end \
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while(0)
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class C;
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C c;
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real r;
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endclass
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initial begin
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C c1, c2;
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c1 = new;
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c1.c = new;
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c2 = c1.c;
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c1.c.r = 12.3;
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`check(c2.r, 12.3);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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