43 lines
650 B
Verilog
43 lines
650 B
Verilog
module top_module();
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wire data_bus; // Bidirectional data bus
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module_a u_module_a (
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.data(data_bus)
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);
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module_b u_module_b (
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.data(data_bus)
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);
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endmodule
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module module_a (
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inout wire data
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);
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// Drive the data bus with 1 when module_a is active
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assign data = 1'b1;
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endmodule
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module module_b (
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inout wire data
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);
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// Read data from the bus
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wire data_in = data;
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// Set data to high impedance to allow other modules to drive the bus
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assign data = 1'bz;
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endmodule
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module tb();
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top_module dut();
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initial begin
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#0;
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if (dut.data_bus === 1'b1)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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