129 lines
4.0 KiB
Verilog
129 lines
4.0 KiB
Verilog
/*
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* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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* $Id: sqrt.v,v 1.1 2003/03/30 03:54:48 stevewilliams Exp $"
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*/
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/*
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* This module approximates the square root of an unsigned 32bit
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* number. The algorithm works by doing a bit-wise binary search.
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* Starting from the most significant bit, the accumulated value
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* tries to put a 1 in the bit position. If that makes the square
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* too big for the input, the bit is left zero, otherwise it is set
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* in the result. This continues for each bit, decreasing in
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* significance, until all the bits are calculated or all the
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* remaining bits are zero.
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*
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* Since the result is an integer, this function really calculates
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* value of the expression:
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*
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* x = floor(sqrt(y))
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*
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* where sqrt(y) is the exact square root of y and floor(N) is the
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* largest integer <= N.
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*
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* For 32bit numbers, this will never run more then 16 iterations,
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* which amounts to 16 clocks.
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*/
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module sqrt32(clk, rdy, reset, x, .y(acc));
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input clk;
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output rdy;
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input reset;
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input [31:0] x;
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output [15:0] acc;
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// acc holds the accumulated result, and acc2 is the accumulated
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// square of the accumulated result.
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reg [15:0] acc;
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reg [31:0] acc2;
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// Keep track of which bit I'm working on.
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reg [4:0] bitl;
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wire [15:0] bit = 1 << bitl;
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wire [31:0] bit2 = 1 << (bitl << 1);
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// The output is ready when the bitl counter underflows.
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wire rdy = bitl[4];
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// guess holds the potential next values for acc, and guess2 holds
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// the square of that guess. The guess2 calculation is a little bit
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// subtle. The idea is that:
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//
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// guess2 = (acc + bit) * (acc + bit)
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// = (acc * acc) + 2*acc*bit + bit*bit
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// = acc2 + 2*acc*bit + bit2
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// = acc2 + 2 * (acc<<bitl) + bit
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//
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// This works out using shifts because bit and bit2 are known to
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// have only a single bit in them.
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wire [15:0] guess = acc | bit;
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wire [31:0] guess2 = acc2 + bit2 + ((acc << bitl) << 1);
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(* ivl_synthesis_on *)
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always @(posedge clk or posedge reset)
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if (reset) begin
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acc = 0;
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acc2 = 0;
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bitl = 15;
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end else begin
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if (guess2 <= x) begin
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acc <= guess;
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acc2 <= guess2;
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end
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bitl <= bitl - 5'd1;
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end
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endmodule // sqrt32
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/*
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* This module represents the chip packaging that we intend to
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* generate. We bind pins here, and route the clock to the global
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* clock buffer.
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*/
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module chip_root(clk, rdy, reset, x, y);
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input clk;
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output rdy;
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input reset;
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input [31:0] x;
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output [15:0] y;
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wire clk_int;
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(* cellref="BUFG:O,I" *)
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buf gbuf (clk_int, clk);
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sqrt32 dut(.clk(clk_int), .reset(reset), .rdy(rdy), .x(x), .y(y));
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/* Assign the clk to GCLK0, which is on pin P39. */
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$attribute(clk, "PAD", "39");
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// We don't care where the remaining pins go, so set the pin number
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// to 0. This tells the implementation tools that we want a PAD,
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// but we don't care which. Also note the use of a comma (,)
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// separated list to assign pins to the bits of a vector.
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$attribute(rdy, "PAD", "0");
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$attribute(reset, "PAD", "0");
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$attribute(x, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
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$attribute(y, "PAD", "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0");
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endmodule // chip_root
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