441 lines
14 KiB
C++
441 lines
14 KiB
C++
#ifndef __pform_H
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#define __pform_H
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/*
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* Copyright (c) 1998-2010 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "netlist.h"
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# include "HName.h"
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# include "named.h"
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# include "Module.h"
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# include "Statement.h"
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# include "AStatement.h"
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# include "PGate.h"
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# include "PExpr.h"
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# include "PTask.h"
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# include "PUdp.h"
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# include "PWire.h"
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# include "verinum.h"
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# include "discipline.h"
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# include <iostream>
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# include <string>
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# include <list>
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# include <memory>
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# include <cstdio>
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/*
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* These classes implement the parsed form (P-form for short) of the
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* original Verilog source. the parser generates the pform for the
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* convenience of later processing steps.
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*/
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/*
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* Wire objects represent the named wires (of various flavor) declared
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* in the source.
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*
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* Gate objects are the functional modules that are connected together
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* by wires.
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*
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* Wires and gates, connected by joints, represent a netlist. The
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* netlist is therefore a representation of the desired circuit.
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*/
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class PGate;
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class PExpr;
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class PSpecPath;
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struct vlltype;
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/*
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* The min:typ:max expression s selected at parse time using the
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* enumeration. When the compiler makes a choice, it also prints a
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* warning if min_typ_max_warn > 0.
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*/
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extern enum MIN_TYP_MAX { MIN, TYP, MAX } min_typ_max_flag;
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extern unsigned min_typ_max_warn;
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PExpr* pform_select_mtm_expr(PExpr*min, PExpr*typ, PExpr*max);
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/*
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* This flag is true if the lexor thinks we are in a library source
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* file.
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*/
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extern bool pform_library_flag;
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/*
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* These type are lexical types -- that is, types that are used as
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* lexical values to decorate the parse tree during parsing. They are
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* not in any way preserved once parsing is done.
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*/
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/* This is information about port name information for named port
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connections. */
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typedef named<PExpr*> named_pexpr_t;
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struct parmvalue_t {
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list<PExpr*>*by_order;
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svector<named_pexpr_t*>*by_name;
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};
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struct str_pair_t { ivl_drive_t str0, str1; };
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struct net_decl_assign_t {
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perm_string name;
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PExpr*expr;
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struct net_decl_assign_t*next;
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};
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/* The lgate is gate instantiation information. */
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struct lgate {
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lgate(int =0)
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: parms(0), parms_by_name(0), file(NULL), lineno(0)
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{ range[0] = 0;
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range[1] = 0;
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}
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string name;
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list<PExpr*>*parms;
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svector<named_pexpr_t*>*parms_by_name;
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PExpr*range[2];
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const char* file;
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unsigned lineno;
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};
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/* Use this function to transform the parted form of the attribute
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list to the attribute map that is used later. */
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extern void pform_bind_attributes(map<perm_string,PExpr*>&attributes,
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svector<named_pexpr_t*>*attr);
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/* The lexor calls this function to change the default nettype. */
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extern void pform_set_default_nettype(NetNet::Type net,
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const char*file,
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unsigned lineno);
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/*
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* Look for the given wire in the current lexical scope. If the wire
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* (including variables of any type) cannot be found in the current
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* scope, then return 0.
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*/
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extern PWire* pform_get_wire_in_scope(perm_string name);
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/*
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* The parser uses startmodule and endmodule together to build up a
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* module as it parses it. The startmodule tells the pform code that a
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* module has been noticed in the source file and the following events
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* are to apply to the scope of that module. The endmodule causes the
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* pform to close up and finish the named module.
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*/
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extern void pform_startmodule(const char*, const char*file, unsigned lineno,
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svector<named_pexpr_t*>*attr);
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extern void pform_check_timeunit_prec();
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extern void pform_module_set_ports(vector<Module::port_t*>*);
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/* This function is used to support the port definition in a
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port_definition_list. In this case, we have everything needed to
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define the port, all in one place. */
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extern void pform_module_define_port(const struct vlltype&li,
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perm_string name,
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NetNet::PortType,
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NetNet::Type type,
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ivl_variable_type_t data_type,
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bool signed_flag,
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list<PExpr*>*range,
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svector<named_pexpr_t*>*attr);
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extern Module::port_t* pform_module_port_reference(perm_string name,
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const char*file,
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unsigned lineno);
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extern void pform_endmodule(const char*, bool inside_celldefine,
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Module::UCDriveType uc_drive_def);
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extern void pform_make_udp(perm_string name, list<perm_string>*parms,
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svector<PWire*>*decl, list<string>*table,
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Statement*init,
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const char*file, unsigned lineno);
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extern void pform_make_udp(perm_string name,
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bool sync_flag, perm_string out_name,
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PExpr*sync_init,
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list<perm_string>*parms,
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list<string>*table,
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const char*file, unsigned lineno);
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/*
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* Enter/exit name scopes. The push_scope function pushes the scope
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* name string onto the scope hierarchy. The pop pulls it off and
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* deletes it. Thus, the string pushed must be allocated.
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*/
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extern void pform_pop_scope();
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extern PTask*pform_push_task_scope(const struct vlltype&loc, char*name,
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bool is_auto);
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extern PFunction*pform_push_function_scope(const struct vlltype&loc, char*name,
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bool is_auto);
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extern PBlock*pform_push_block_scope(char*name, PBlock::BL_TYPE tt);
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extern void pform_put_behavior_in_scope(AProcess*proc);
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extern verinum* pform_verinum_with_size(verinum*s, verinum*val,
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const char*file, unsigned lineno);
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/*
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* This function takes the list of names as new genvars to declare in
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* the current module or generate scope.
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*/
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extern void pform_genvars(const struct vlltype&li, list<perm_string>*names);
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extern void pform_start_generate_for(const struct vlltype&li,
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char*ident1,
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PExpr*init,
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PExpr*test,
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char*ident2,
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PExpr*next);
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extern void pform_start_generate_if(const struct vlltype&li, PExpr*test);
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extern void pform_start_generate_else(const struct vlltype&li);
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extern void pform_start_generate_case(const struct vlltype&lp, PExpr*test);
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extern void pform_start_generate_nblock(const struct vlltype&lp, char*name);
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extern void pform_generate_case_item(const struct vlltype&lp, list<PExpr*>*test);
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extern void pform_generate_block_name(char*name);
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extern void pform_endgenerate();
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/*
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* This function returns the lexically containing generate scheme, if
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* there is one. The parser may use this to check if we are within a
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* generate scheme.
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*/
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extern PGenerate* pform_parent_generate(void);
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/*
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* The makewire functions announce to the pform code new wires. These
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* go into a module that is currently opened.
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*/
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extern void pform_makewire(const struct vlltype&li, perm_string name,
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NetNet::Type type,
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NetNet::PortType pt,
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ivl_variable_type_t,
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svector<named_pexpr_t*>*attr);
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/* This form handles simple declarations */
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extern void pform_makewire(const struct vlltype&li,
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list<PExpr*>*range,
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bool signed_flag,
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list<perm_string>*names,
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NetNet::Type type,
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NetNet::PortType,
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ivl_variable_type_t,
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svector<named_pexpr_t*>*attr,
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PWSRType rt = SR_NET);
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/* This form handles assignment declarations. */
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extern void pform_makewire(const struct vlltype&li,
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list<PExpr*>*range,
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bool signed_flag,
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list<PExpr*>*delay,
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str_pair_t str,
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net_decl_assign_t*assign_list,
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NetNet::Type type,
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ivl_variable_type_t);
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extern void pform_make_reginit(const struct vlltype&li,
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perm_string name, PExpr*expr);
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/* Look up the names of the wires, and set the port type,
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i.e. input, output or inout. If the wire does not exist, create
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it. The second form takes a single name. */
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extern void pform_set_port_type(const struct vlltype&li,
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list<perm_string>*names,
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list<PExpr*>*range,
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bool signed_flag,
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NetNet::PortType);
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extern void pform_set_port_type(perm_string nm, NetNet::PortType pt,
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const char*file, unsigned lineno);
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extern void pform_set_net_range(list<perm_string>*names,
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list<PExpr*>*,
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bool signed_flag,
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ivl_variable_type_t,
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PWSRType rt = SR_NET);
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extern void pform_set_reg_idx(perm_string name, PExpr*l, PExpr*r);
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extern void pform_set_reg_integer(list<perm_string>*names);
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extern void pform_set_reg_time(list<perm_string>*names);
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extern void pform_set_integer_2atom(uint64_t width, bool signed_flag, list<perm_string>*names);
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extern void pform_set_enum(const struct vlltype&li, enum_type_t*enum_type, list<perm_string>*names);
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/* pform_set_attrib and pform_set_type_attrib exist to support the
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$attribute syntax, which can only set string values to
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attributes. The functions keep the value strings that are
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passed in. */
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extern void pform_set_attrib(perm_string name, perm_string key,
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char*value);
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extern void pform_set_type_attrib(perm_string name, const string&key,
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char*value);
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extern LexicalScope::range_t* pform_parameter_value_range(bool exclude_flag,
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bool low_open, PExpr*low_expr,
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bool hig_open, PExpr*hig_expr);
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extern void pform_set_parameter(const struct vlltype&loc,
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perm_string name,
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ivl_variable_type_t type,
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bool signed_flag,
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list<PExpr*>*range,
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PExpr*expr, LexicalScope::range_t*value_range);
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extern void pform_set_localparam(const struct vlltype&loc,
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perm_string name,
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ivl_variable_type_t type,
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bool signed_flag,
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list<PExpr*>*range,
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PExpr*expr);
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extern void pform_set_defparam(const pform_name_t&name, PExpr*expr);
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/*
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* Functions related to specify blocks.
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*/
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extern void pform_set_specparam(perm_string name, PExpr*expr);
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extern PSpecPath*pform_make_specify_path(const struct vlltype&li,
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list<perm_string>*src, char pol,
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bool full_flag, list<perm_string>*dst);
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extern PSpecPath*pform_make_specify_edge_path(const struct vlltype&li,
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int edge_flag, /*posedge==true */
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list<perm_string>*src, char pol,
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bool full_flag, list<perm_string>*dst,
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PExpr*data_source_expression);
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extern PSpecPath*pform_assign_path_delay(PSpecPath*obj, list<PExpr*>*delays);
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extern void pform_module_specify_path(PSpecPath*obj);
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/*
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* pform_make_behavior creates processes that are declared with always
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* or initial items.
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*/
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extern PProcess* pform_make_behavior(ivl_process_type_t, Statement*,
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svector<named_pexpr_t*>*attr);
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extern svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*);
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extern void pform_make_events(list<perm_string>*names,
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const char*file, unsigned lineno);
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/*
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* Make real datum objects.
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*/
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extern void pform_make_reals(list<perm_string>*names,
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const char*file, unsigned lineno);
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/*
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* The makegate function creates a new gate (which need not have a
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* name) and connects it to the specified wires.
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*/
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extern void pform_makegates(PGBuiltin::Type type,
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struct str_pair_t str,
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list<PExpr*>*delay,
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svector<lgate>*gates,
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svector<named_pexpr_t*>*attr);
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extern void pform_make_modgates(perm_string type,
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struct parmvalue_t*overrides,
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svector<lgate>*gates);
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/* Make a continuous assignment node, with optional bit- or part- select. */
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extern void pform_make_pgassign_list(list<PExpr*>*alist,
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list<PExpr*>*del,
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struct str_pair_t str,
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const char* fn, unsigned lineno);
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/* Given a port type and a list of names, make a list of wires that
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can be used as task port information. */
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extern svector<PWire*>*pform_make_task_ports(NetNet::PortType pt,
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ivl_variable_type_t vtype,
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bool signed_flag,
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list<PExpr*>*range,
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list<perm_string>*names,
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const char* file,
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unsigned lineno);
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/*
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* These are functions that the outside-the-parser code uses the do
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* interesting things to the Verilog. The parse function reads and
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* parses the source file and places all the modules it finds into the
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* mod list. The dump function dumps a module to the output stream.
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*/
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extern void pform_dump(ostream&out, Module*mod);
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/*
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* Used to report the original module location when a nested module
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* (missing endmodule) is found by the parser.
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*/
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extern void pform_error_nested_modules();
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/* ** pform_discipline.cc
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* Functions for handling the parse of natures and disciplines. These
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* functions are in pform_disciplines.cc
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*/
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extern void pform_start_nature(const char*name);
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extern void pform_end_nature(const struct vlltype&loc);
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extern void pform_nature_access(const struct vlltype&loc, const char*name);
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extern void pform_start_discipline(const char*name);
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extern void pform_end_discipline(const struct vlltype&loc);
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extern void pform_discipline_domain(const struct vlltype&loc, ivl_dis_domain_t use_domain);
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extern void pform_discipline_potential(const struct vlltype&loc, const char*name);
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extern void pform_discipline_flow(const struct vlltype&loc, const char*name);
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extern void pform_attach_discipline(const struct vlltype&loc,
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ivl_discipline_t discipline, list<perm_string>*names);
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extern void pform_dump(ostream&out, const ivl_nature_s*);
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extern void pform_dump(ostream&out, const ivl_discipline_s*);
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/* ** pform_analog.cc
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*/
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extern void pform_make_analog_behavior(const struct vlltype&loc,
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ivl_process_type_t type, Statement*st);
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extern AContrib*pform_contribution_statement(const struct vlltype&loc,
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PExpr*lval, PExpr*rval);
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extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc,
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char*name, char*n1, char*n2);
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extern PExpr* pform_make_branch_probe_expression(const struct vlltype&loc,
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char*name, char*branch);
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/*
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* Parse configuration file with format <key>=<value>, where key
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* is the hierarchical name of a valid parameter name and value
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* is the value user wants to assign to. The value should be constant.
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*/
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extern void parm_to_defparam_list(const string¶m);
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/*
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* Tasks to set the timeunit or timeprecision for SystemVerilog.
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*/
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extern void pform_set_timeunit(const char*txt, bool in_module, bool only_check);
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extern void pform_set_timeprecision(const char*txt, bool in_module,
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bool only_check);
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#endif
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