iverilog/ivtest/gold/vcd-dup.vcd.gold

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$date
Sun May 15 15:15:18 2022
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module test $end
$var wire 1 ! c2 $end
$var wire 1 " c1 $end
$var reg 1 # a $end
$var reg 1 $ b1 $end
$var reg 1 % b2 $end
$scope module m1 $end
$var wire 1 # a $end
$var wire 1 $ b $end
$var wire 1 " c $end
$var wire 1 & c2 $end
$var wire 1 ' c1 $end
$upscope $end
$scope module m2 $end
$var wire 1 # a $end
$var wire 1 % b $end
$var wire 1 ! c $end
$var wire 1 ( c2 $end
$var wire 1 ) c1 $end
$upscope $end
$scope task set $end
$var reg 3 * bits [2:0] $end
$var reg 1 + t1 $end
$upscope $end
$upscope $end
$scope module test $end
$scope module m1 $end
$scope module mm1 $end
$var wire 1 , c1 $end
$upscope $end
$upscope $end
$upscope $end
$scope module test $end
$scope module m1 $end
$scope module mm1 $end
$var wire 1 - a $end
$var wire 1 ' c $end
$upscope $end
$scope module mm2 $end
$var wire 1 . a $end
$var wire 1 & c $end
$var wire 1 / c1 $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
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$end
#1
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#2
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#4
b1 *
#5
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#7
b10 *
#8
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#9
$dumpoff
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$end
#15
$dumpon
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$end
#16
1+
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#17
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1%
#19
b110 *
#20
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#22
b111 *
#23
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1%
#25
b0 *
#26
1'
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#27
$dumpall
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$end
#28