5ef847ea87
SystemVerilog supports type parameters. These are similar to value parameters, but they allow to pass a type to a module or similar when instantiating it. E.g. ``` module A #(parameter type T = int); endmodule module B; A #(.T(real)) i_a; endmodule ``` Add support for handling type parameters. For the vlog95 and vhdl backends type parameters, similar to typedefs, get replaced with their actual value. For modules with non-local type parameters for each module instance a unique module or architecture is generated with the actual type. Querying type parameters through VPI is not yet supported. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
|---|---|---|
| .. | ||
| vhpi | ||
| Makefile.in | ||
| cast.cc | ||
| cppcheck.sup | ||
| expr.cc | ||
| logic.cc | ||
| lpm.cc | ||
| process.cc | ||
| scope.cc | ||
| state.cc | ||
| state.hh | ||
| stmt.cc | ||
| support.cc | ||
| support.hh | ||
| vhdl-s.conf | ||
| vhdl.cc | ||
| vhdl.conf | ||
| vhdl_config.h.in | ||
| vhdl_element.cc | ||
| vhdl_element.hh | ||
| vhdl_helper.hh | ||
| vhdl_syntax.cc | ||
| vhdl_syntax.hh | ||
| vhdl_target.h | ||
| vhdl_type.cc | ||
| vhdl_type.hh | ||