210 lines
6.7 KiB
C
210 lines
6.7 KiB
C
/*
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* Copyright (c) 2003 Stephen Williams (steve at icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.c,v 1.1 2003/04/05 05:53:34 steve Exp $"
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#endif
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# include "xilinx.h"
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edif_cell_t xilinx_cell_buf(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "BUF", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "BUFG", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "IBUF", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_inv(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "INV", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "OBUF", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "LUT2", 3);
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edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "LUT3", 4);
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edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "LUT4", 5);
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edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, LUT_I3, "I3", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "FDCE", 5);
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edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "FDCPE", 6);
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edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, FDCE_PRE,"PRE", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "MULT_AND", 3);
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edif_cell_portconfig(cell, MULT_AND_LO, "LO", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MULT_AND_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MULT_AND_I1, "I1", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "MUXCY", 4);
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edif_cell_portconfig(cell, MUXCY_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXCY_S, "S", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "MUXCY_L", 4);
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edif_cell_portconfig(cell, MUXCY_O, "LO", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MUXCY_S, "S", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell != 0) return cell;
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cell = edif_xcell_create(xlib, "XORCY", 3);
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edif_cell_portconfig(cell, XORCY_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, XORCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, XORCY_LI, "LI", IVL_SIP_INPUT);
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return cell;
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}
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/*
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* $Log: xilinx.c,v $
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* Revision 1.1 2003/04/05 05:53:34 steve
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* Move library cell management to common file.
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*
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*/
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