56 lines
1.0 KiB
Verilog
56 lines
1.0 KiB
Verilog
module main;
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reg [2:0] ADDR;
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wire [1:0] data0 = 0, data1 = 1, data2 = 2, data3 = 3;
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reg [1:0] data;
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always @*
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case (ADDR[2:0])
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3'b000: data = data0;
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3'b001: data = data1;
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3'b010: data = data2;
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3'b011: data = data3;
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default: data = 0;
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endcase // case(ADDR[2:0])
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initial begin
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ADDR = 0;
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#1 $display("data=%b", data);
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if (data !== ADDR) begin
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$display("FAILED");
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$finish;
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end
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ADDR = 1;
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#1 $display("data=%b", data);
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if (data !== ADDR) begin
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$display("FAILED");
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$finish;
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end
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ADDR = 2;
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#1 $display("data=%b", data);
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if (data !== ADDR) begin
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$display("FAILED");
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$finish;
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end
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ADDR = 3;
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#1 $display("data=%b", data);
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if (data !== ADDR) begin
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$display("FAILED");
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$finish;
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end
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ADDR = 4;
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#1 $display("data=%b", data);
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if (data !== 0)begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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