83 lines
1.9 KiB
Verilog
83 lines
1.9 KiB
Verilog
module test #(
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parameter integer i1 = 1.0, i2 = 2,
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parameter [7:0] v1 = 3.0, v2 = 4,
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parameter real r1 = 5.0, r2 = 6,
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parameter u1 = 7.0, u2 = 8'd8
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)(
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);
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parameter integer i3 = 1.0, i4 = 2;
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parameter [7:0] v3 = 3.0, v4 = 4;
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parameter real r3 = 5.0, r4 = 6;
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parameter u3 = 7.0, u4 = 8'd8;
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localparam integer i5 = 1.0, i6 = 2;
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localparam [7:0] v5 = 3.0, v6 = 4;
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localparam real r5 = 5.0, r6 = 6;
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localparam u5 = 7.0, u6 = 8'd8;
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reg failed = 0;
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initial begin
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$display("%b", i1);
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$display("%b", i2);
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$display("%b", v1);
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$display("%b", v2);
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$display("%f", r1);
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$display("%f", r2);
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$display("%f", u1);
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$display("%b", u2);
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if (i1 !== 32'd1) failed = 1;
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if (i2 !== 32'd2) failed = 1;
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if (v1 !== 8'd3) failed = 1;
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if (v2 !== 8'd4) failed = 1;
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if (r1 != 5.0) failed = 1;
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if (r2 != 6.0) failed = 1;
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if (u1 != 7.0) failed = 1;
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if (u2 !== 8'd8) failed = 1;
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$display("%b", i3);
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$display("%b", i4);
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$display("%b", v3);
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$display("%b", v4);
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$display("%f", r3);
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$display("%f", r4);
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$display("%f", u3);
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$display("%b", u4);
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if (i3 !== 32'd1) failed = 1;
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if (i4 !== 32'd2) failed = 1;
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if (v3 !== 8'd3) failed = 1;
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if (v4 !== 8'd4) failed = 1;
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if (r3 != 5.0) failed = 1;
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if (r4 != 6.0) failed = 1;
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if (u3 != 7.0) failed = 1;
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if (u4 !== 8'd8) failed = 1;
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$display("%b", i5);
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$display("%b", i6);
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$display("%b", v5);
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$display("%b", v6);
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$display("%f", r5);
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$display("%f", r6);
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$display("%f", u5);
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$display("%b", u6);
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if (i5 !== 32'd1) failed = 1;
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if (i6 !== 32'd2) failed = 1;
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if (v5 !== 8'd3) failed = 1;
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if (v6 !== 8'd4) failed = 1;
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if (r5 != 5.0) failed = 1;
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if (r6 != 6.0) failed = 1;
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if (u5 != 7.0) failed = 1;
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if (u6 !== 8'd8) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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