69 lines
1.7 KiB
Verilog
69 lines
1.7 KiB
Verilog
module top;
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reg pass;
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enum bit signed [7:0] {a = 1, b = 2, c = 3, d = 4} enum_var;
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initial begin
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pass = 1'b1;
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// Add another test that a negative value is not valid.
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// Also an out of range value stays out of range.
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enum_var = a;
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if (enum_var !== enum_var.first) begin
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$display("FAILED: initialization, expected %d, got %d", a, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.next;
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enum_var = enum_var.prev;
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enum_var = enum_var.next();
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if (enum_var !== b) begin
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$display("FAILED: next(), expected %d, got %d", b, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.next(0);
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if (enum_var !== b) begin
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$display("FAILED: next(0), expected %d, got %d", b, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.next(1);
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if (enum_var !== c) begin
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$display("FAILED: next(1), expected %d, got %d", c, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.next(2);
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if (enum_var !== a) begin
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$display("FAILED: next(2), expected %d, got %d", a, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.prev();
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if (enum_var !== d) begin
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$display("FAILED: prev(), expected %d, got %d", d, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.prev(0);
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if (enum_var !== d) begin
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$display("FAILED: prev(0), expected %d, got %d", d, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.prev(1);
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if (enum_var !== c) begin
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$display("FAILED: prev(1), expected %d, got %d", c, enum_var);
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pass = 1'b0;
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end
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enum_var = enum_var.prev(2);
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if (enum_var !== a) begin
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$display("FAILED: prev(2), expected %d, got %d", a, enum_var);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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