43 lines
1.0 KiB
Verilog
43 lines
1.0 KiB
Verilog
module top;
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reg passed;
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// These should be OK
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enum {zdef1_[0:1]} zdef1;
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enum {zdef2_[1:0]} zdef2;
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enum {zdefb_[0:0]} zdef3;
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enum {zvalb_[0:0] = 1} zval1;
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initial begin
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passed = 1'b1;
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if (zdef1_0 !== 0) begin
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$display("FAILED: expected zdef1_0 to be 0, got %0d", zdef1_0);
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passed = 1'b0;
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end
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if (zdef1_1 !== 1) begin
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$display("FAILED: expected zdef1_1 to be 1, got %0d", zdef1_1);
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passed = 1'b0;
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end
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if (zdef2_1 !== 0) begin
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$display("FAILED: expected zdef2_1 to be 0, got %0d", zdef2_1);
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passed = 1'b0;
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end
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if (zdef2_0 !== 1) begin
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$display("FAILED: expected zdef2_0 to be 1, got %0d", zdef2_0);
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passed = 1'b0;
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end
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if (zdefb_0 !== 0) begin
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$display("FAILED: expected zdefb_0 to be 0, got %0d", zdefb_0);
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passed = 1'b0;
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end
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if (zvalb_0 !== 1) begin
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$display("FAILED: expected zvalb_0 to be 1, got %0d", zvalb_0);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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