28 lines
729 B
Verilog
28 lines
729 B
Verilog
module top;
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// An undefined sequence value is an error.
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enum {udef[1'bx]} udef1;
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enum {udef1[1'bx:1]} udef2;
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enum {udef2[1:1'bx]} udef3;
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enum {udefb[1'bx:1'bx]} udef4;
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enum {uval[1'bx] = 1} uval1;
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enum {uval1[1'bx:1] = 1} uval2;
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enum {uval2[1:1'bx] = 1} uval3;
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enum {uvalb[1'bx:1'bx] = 1} uval4;
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// A zero sequence value is an error.
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enum {zdef[0]} zdef1;
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enum {zval[0] = 1} zval1;
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// A negative sequence value is an error.
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enum {ndef[-1]} ndef1;
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enum {ndef1[-1:0]} ndef2;
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enum {ndef2[0:-1]} ndef3;
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enum {ndefb[-1:-1]} ndef4;
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enum {nval[-1] = 1} nval1;
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enum {nval1[-1:0] = 1} nval2;
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enum {nval2[0:-1] = 1} nval3;
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enum {nvalb[-1:-1] = 1} nval4;
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initial $display("FAILED");
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endmodule
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