29 lines
392 B
Verilog
29 lines
392 B
Verilog
module top();
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reg foo;
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tri [1:0] a;
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tri [1:0] b;
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tri [3:0] c;
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assign a[0] = foo;
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tran t1(a[0], a[1]);
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tran t2(b[0], b[1]);
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tran t3[1:0](a, c[1:0]);
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tran t4[1:0](b, c[3:2]);
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tran t5(c[1], c[3]);
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initial begin
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foo = 1'b1;
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#1 $display("%b %b %b", a, b, c);
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if ((a === 2'b11) && (b === 2'b11) && (c === 4'b1111))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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