20 lines
481 B
Verilog
20 lines
481 B
Verilog
module top;
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reg [23:0] in1;
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reg [54:0] in2;
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initial begin
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in1 = 24'b111111000000111111000000;
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in2 = 55'b0000011111000001111100000111110000011111000001111100000;
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#1;
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if (dut.arg !== 96'b111111000000111111000000zzzzzzzzzzzzzzzzz0000011111000001111100000111110000011111000001111100000) begin
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$display("FAILED");
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end else $display("PASSED");
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end
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test dut(in1, in2);
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endmodule
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module test(arg[119:96], arg[78:24]);
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input [119:24] arg;
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endmodule
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