51 lines
1.1 KiB
Verilog
51 lines
1.1 KiB
Verilog
module test;
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reg signed [3:0] a;
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reg signed [3:0] b;
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reg [3:0] u;
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reg [3:0] r;
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reg fail;
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initial begin
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fail = 0;
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a = 4'b1000;
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b = 4'b0010;
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u = 4'b0001;
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r = ((a >>> 1) | b ) | u;
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$display("step 1 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((4'b1000 >>> 1) | b ) | u;
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$display("step 2 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((a >>> 1) | 4'b0010) | u;
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$display("step 3 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((a >>> 1) | b ) | 4'b0001;
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$display("step 4 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((4'b1000 >>> 1) | 4'b0010) | u;
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$display("step 5 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((a >>> 1) | 4'b0010) | 4'b0001;
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$display("step 6 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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r = ((4'b1000 >>> 1) | 4'b0010) | 4'b0001;
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$display("step 7 expected '0111', got '%b'", r);
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if (r !== 4'b0111) fail = 1;
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if (fail)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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