14 lines
406 B
Verilog
14 lines
406 B
Verilog
module top;
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reg [3:0] val;
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initial begin
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val = 4'b1111;
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// The 'b0 should have a minimum size of integer width. This implies
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// that val should be zero extended before it is inverted. Making
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// this a false expression. See 1364-2005 (3.5.1 for width and 5.4
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// for how the width is propagated.
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if (~val == 'b0) $display("Failed.");
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else $display("PASSED");
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end
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endmodule
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