50 lines
1.2 KiB
Verilog
50 lines
1.2 KiB
Verilog
// Icarus has a number of places where it can calculate %.
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module top;
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parameter out0 = 64'shF333333333333392 % 3'sd3;
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reg passed;
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wire signed [63:0] in;
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wire signed [2:0] const_w0;
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reg signed [63:0] out1;
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wire signed [63:0] out2;
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reg signed [63:0] out3;
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assign in = 64'hF333333333333392;
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assign const_w0 = 3'sd3;
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always @* begin
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out1 = (in % const_w0);
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end
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assign out2 = (in % const_w0);
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initial begin
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passed = 1'b1;
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#1;
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$display("Testing %0d %% %0d.", in, const_w0);
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// Check the parameter result.
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if (out0 !== -2) begin
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$display("Failed: constant %%, expected -2, got %0d.", out0);
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passed = 1'b0;
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end
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// Check the always result.
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if (out1 !== -2) begin
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$display("Failed: procedural %%, expected -2, got %0d.", out1);
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passed = 1'b0;
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end
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// Check the CA result.
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if (out2 !== -2) begin
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$display("Failed: CA %%, expected -2, got %0d.", out2);
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passed = 1'b0;
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end
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// Check a compile time constant result.
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out3 = 64'shF333333333333392 % 3'sd3;
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if (out3 !== -2) begin
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$display("Failed: CA %%, expected -2, got %0d.", out3);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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$finish;
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end
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endmodule
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