75 lines
1.9 KiB
Verilog
75 lines
1.9 KiB
Verilog
`timescale 1ns/100ps
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module top;
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reg pass;
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reg in;
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wire out_bit;
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wire [3:0] out_vec, out_arr;
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wire real r_bit, r_vec;
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wire real r_arr[1:0];
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initial begin
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pass = 1'b1;
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in <= 1'b0;
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#1 in = 1'b1;
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#0.5 in = 1'b0;
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#0.5 in = 1'b1;
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#0.5 in = 1'b0;
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#0.5 in = 1'b1;
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#0.5 in = 1'b0;
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#0.5 in = 1'b1;
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#1 if (pass) $display("PASSED");
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end
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real_to_xx u1(out_bit, in);
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always @(out_bit) if (out_bit !== ($stime % 2)) begin
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$display("Failed real_to_xx, got %b, expected %1b", out_bit, $stime%2);
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pass = 1'b0;
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end
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real_to_xx u2(out_vec, in);
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always @(out_vec) if (out_vec !== $stime) begin
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$display("Failed real_to_xx(vec), got %b, expected %2b", out_vec, $stime);
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pass = 1'b0;
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end
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real_to_xx u3[1:0](out_arr, in);
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always @(out_arr) #0.1 if ((out_arr[1:0] !== ($stime % 4)) &&
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(out_arr[3:2] !== ($stime % 4))) begin
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$display("Failed real_to_xx[1:0], got %b, expected %2b%2b", out_arr,
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$stime%4, $stime%4);
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pass = 1'b0;
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end
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bit_to_real u4(r_bit, in);
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always @(r_bit) if (r_bit != ($stime % 2)) begin
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$display("Failed bit_to_real, got %f, expected %1b", r_bit, $stime%2);
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pass = 1'b0;
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end
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vec_to_real u5(r_vec, in);
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always @(r_vec) if (r_vec != $stime) begin
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$display("Failed vec_to_real, got %f, expected %1b", r_vec, $stime);
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pass = 1'b0;
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end
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endmodule
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// Check a real value going to a various things.
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module real_to_xx (output wire real out, input wire in);
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real rval;
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assign out = rval;
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always @(posedge in) rval = rval + 1;
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endmodule
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module bit_to_real (output wire out, input wire in);
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reg rval = 0;
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assign out = rval;
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always @(posedge in) rval = rval + 1;
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endmodule
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module vec_to_real (output wire [3:0] out, input wire in);
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reg [3:0] rval = 0;
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assign out = rval;
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always @(posedge in) rval = rval + 1;
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endmodule
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