94 lines
2.5 KiB
Verilog
94 lines
2.5 KiB
Verilog
module top;
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reg pass;
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reg [3:0] val;
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reg [3:0] pv_val;
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real rval;
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initial begin
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pass = 1'b1;
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// A release of an unforced variable should not change the variable.
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val = 4'b0110;
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release val;
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if (val !== 4'b0110) begin
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$display("Failed release of unforced sig, expected 4'b0110, got %b",
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val);
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pass = 1'b0;
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end
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// Verify that a force/release leaves the variable set correctly.
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force val = 4'b1001;
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release val;
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if (val !== 4'b1001) begin
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$display("Failed release of forced sig, expected 4'b1001, got %b",
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val);
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pass = 1'b0;
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end
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// A release of a currently unforced varaible should not change it.
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val = 4'b0110;
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release val;
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if (val !== 4'b0110) begin
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$display("Failed release of unforced sig(2), expected 4'b0110, got %b",
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val);
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pass = 1'b0;
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end
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// A release of an unforced variable should not change the variable.
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pv_val = 4'b1001;
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release pv_val[1];
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if (pv_val !== 4'b1001) begin
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$display("Failed pv release of unforced sig, expected 4'b1001, got %b",
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pv_val);
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pass = 1'b0;
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end
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// Verify that a force/release leaves the variable set correctly.
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force pv_val[1] = 1'b1;
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release pv_val[2:0];
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if (pv_val !== 4'b1011) begin
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$display("Failed pv release of forced sig, expected 4'b1011, got %b",
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pv_val);
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pass = 1'b0;
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end
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// A release of a currently unforced varaible should not change it.
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pv_val = 4'b1001;
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release pv_val[1];
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if (pv_val !== 4'b1001) begin
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$display("Failed pv release of unforced sig(2), expected 4'b1001, got %b",
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pv_val);
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pass = 1'b0;
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end
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// A release of an unforced variable should not change the variable.
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rval = 1.0;
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release rval;
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if (rval != 1.0) begin
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$display("Failed release of unforced sig, expected 1.0, got %.1f",
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rval);
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pass = 1'b0;
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end
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// Verify that a force/release leaves the variable set correctly.
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force rval = 2.0;
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release rval;
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if (rval != 2.0) begin
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$display("Failed release of forced sig, expected 2.0, got %.1f",
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rval);
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pass = 1'b0;
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end
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// A release of a currently unforced varaible should not change it.
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rval = 1.0;
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release rval;
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if (rval != 1.0) begin
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$display("Failed release of unforced sig(2), expected 1.0, got %.1f",
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rval);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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