38 lines
679 B
Verilog
38 lines
679 B
Verilog
`timescale 1ns/10ps
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module top;
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reg pass;
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reg a;
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reg p;
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wire y;
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supply1 vdd;
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supply0 gnd;
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tranif1 #(5) nmos_0(gnd, y, a);
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tranif0 #(5) pmos_0(y, vdd, a);
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initial begin
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$monitor($realtime,, y,, a);
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pass = 1'b1;
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p = 1'bx;
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a <= 1'b0;
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repeat (2) #10 a = ~a;
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#10;
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if (pass) $display("PASSED");
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$finish;
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end
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always @(a) begin
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#4.99 if (y !== p) begin
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$display("Failed at %.2f (early), expected %b, got %b", $realtime, p, y);
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pass = 1'b0;
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end
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#0.02 if (y !== ~a) begin
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$display("Failed at %.2f (late), expected %b, got %b", $realtime, ~a, y);
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pass = 1'b0;
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end
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p = y;
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end
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endmodule
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