29 lines
531 B
Verilog
29 lines
531 B
Verilog
module bug;
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reg pass;
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reg Select;
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reg signed [3:0] Delta;
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reg signed [5:0] Value;
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wire signed [5:0] Value_ca = (Select ? 12 : 8) + Delta;
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initial begin
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pass = 1'b1;
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Select = 1;
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Delta = -7;
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Value = (Select ? 12 : 8) + Delta;
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if (Value !== 5) begin
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$display("FAILED: procedural assign, expected 5, got %d", Value);
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pass = 1'b0;
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end
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#1;
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if (Value_ca !== 5) begin
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$display("FAILED: continuous assign, expected 5, got %d", Value_ca);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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