25 lines
653 B
Verilog
25 lines
653 B
Verilog
module foo ();
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parameter CLOCK_FREQUENCY = 90e6;
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// CLOCK_PERIOD_BIT_WIDTH <= log2(90e6)
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// log2(90e6) = 26.423
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parameter CLOCK_PERIOD_BIT_WIDTH = 26;
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// build something big enaugh to hold CLOCK_FREQUENCY x CLOCK_PERIOD_BIT_WIDTH sums.
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parameter CP_SUM_BIT_WIDTH = 2 * CLOCK_PERIOD_BIT_WIDTH;
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//
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// calculate a sane reset value.
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//
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wire [CLOCK_PERIOD_BIT_WIDTH-1:0] rst, rst2;
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assign rst = {1'd1, {CP_SUM_BIT_WIDTH-1 {1'd0}}} / CLOCK_FREQUENCY;
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assign rst2 = (52'd2**(CP_SUM_BIT_WIDTH-1)) / CLOCK_FREQUENCY;
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initial
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#1 if (rst == rst2) $display("PASSED");
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else $display("FAILED");
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endmodule // foo
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