32 lines
502 B
Verilog
32 lines
502 B
Verilog
module pr2837451();
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// this code provides a regression test that exercises
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// vvp_fun_part_sa::recv_vec4_pv
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reg [3:0] a;
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wire [7:0] b;
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wire [3:0] c;
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wire [3:0] d;
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wire [3:0] e;
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assign b[5:2] = a;
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assign c = b[4:1];
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assign d = b[5:2];
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assign e = b[6:3];
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initial begin
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a = 4'b0101;
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#1;
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$display("%b %b %b %b %b", a, b, c, d, e);
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if ((b === 8'bzz0101zz)
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&& (c === 4'b101z)
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&& (d === 4'b0101)
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&& (e === 4'bz010))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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