19 lines
321 B
Verilog
19 lines
321 B
Verilog
module test (a, b);
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output a;
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reg a = 1'b0;
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output reg b = 1'b1;
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endmodule
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module top;
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wire out1, out2;
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test dut(out1, out2);
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initial begin
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#1;
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if (out1 !== 1'b0 || out2 !== 1'b1) begin
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$display("Failed: expected 0:1, got %b:%b", out1, out2);
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end else $display("PASSED");
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end
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endmodule
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