96 lines
2.8 KiB
Verilog
96 lines
2.8 KiB
Verilog
/* The original test case submitted for pr2715558 should not have
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given the the results the bug reporter expected (see pr2986806).
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This is a reworked version that does give those results.
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*/
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module pr2715558b();
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wire sup1_sup0;
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wire sup1_str0;
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wire sup1_pl0;
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wire sup1_we0;
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assign (supply0, supply1) sup1_sup0 = 1'b1;
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assign (supply0, supply1) sup1_sup0 = 1'b0;
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assign (supply0, supply1) sup1_str0 = 1'b1;
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assign (strong0, strong1) sup1_str0 = 1'b0;
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assign (supply0, supply1) sup1_pl0 = 1'b1;
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assign (pull0, pull1) sup1_pl0 = 1'b0;
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assign (supply0, supply1) sup1_we0 = 1'b1;
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assign (weak0, weak1) sup1_we0 = 1'b0;
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initial begin
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#1;
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$display("sup1_sup0 resulted in: %b", sup1_sup0);
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$display("sup1_str0 resulted in: %b", sup1_str0);
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$display("sup1_pl0 resulted in: %b", sup1_pl0);
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$display("sup1_we0 resulted in: %b", sup1_we0);
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end
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wire str1_sup0;
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wire str1_str0;
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wire str1_pl0;
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wire str1_we0;
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assign (strong0, strong1) str1_sup0 = 1'b1;
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assign (supply0, supply1) str1_sup0 = 1'b0;
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assign (strong0, strong1) str1_str0 = 1'b1;
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assign (strong0, strong1) str1_str0 = 1'b0;
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assign (strong0, strong1) str1_pl0 = 1'b1;
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assign (pull0, pull1) str1_pl0 = 1'b0;
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assign (strong0, strong1) str1_we0 = 1'b1;
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assign (weak0, weak1) str1_we0 = 1'b0;
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initial begin
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#1;
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$display("str1_sup0 resulted in: %b", str1_sup0);
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$display("str1_str0 resulted in: %b", str1_str0);
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$display("str1_pl0 resulted in: %b", str1_pl0);
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$display("str1_we0 resulted in: %b", str1_we0);
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end
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wire pl1_sup0;
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wire pl1_str0;
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wire pl1_pl0;
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wire pl1_we0;
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assign (pull0, pull1) pl1_sup0 = 1'b1;
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assign (supply0, supply1) pl1_sup0 = 1'b0;
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assign (pull0, pull1) pl1_str0 = 1'b1;
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assign (strong0, strong1) pl1_str0 = 1'b0;
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assign (pull0, pull1) pl1_pl0 = 1'b1;
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assign (pull0, pull1) pl1_pl0 = 1'b0;
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assign (pull0, pull1) pl1_we0 = 1'b1;
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assign (weak0, weak1) pl1_we0 = 1'b0;
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initial begin
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#1;
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$display("pl1_sup0 resulted in: %b", pl1_sup0);
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$display("pl1_str0 resulted in: %b", pl1_str0);
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$display("pl1_pl0 resulted in: %b", pl1_pl0);
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$display("pl1_we0 resulted in: %b", pl1_we0);
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end
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wire we1_sup0;
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wire we1_str0;
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wire we1_pl0;
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wire we1_we0;
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assign (weak0, weak1) we1_sup0 = 1'b1;
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assign (supply0, supply1) we1_sup0 = 1'b0;
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assign (weak0, weak1) we1_str0 = 1'b1;
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assign (strong0, strong1) we1_str0 = 1'b0;
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assign (weak0, weak1) we1_pl0 = 1'b1;
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assign (pull0, pull1) we1_pl0 = 1'b0;
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assign (weak0, weak1) we1_we0 = 1'b1;
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assign (weak0, weak1) we1_we0 = 1'b0;
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initial begin
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#1;
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$display("we1_sup0 resulted in: %b", we1_sup0);
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$display("we1_str0 resulted in: %b", we1_str0);
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$display("we1_pl0 resulted in: %b", we1_pl0);
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$display("we1_we0 resulted in: %b", we1_we0);
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end
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endmodule
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