45 lines
967 B
Verilog
45 lines
967 B
Verilog
module top;
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reg pass;
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reg [1:0] in, shift, result;
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reg signed [1:0] ins;
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initial begin
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pass = 1'b1;
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in = 2'b01;
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shift = 2'bx1;
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result = in << shift;
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if (result !== 2'bxx) begin
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$display("Failed <<, expected 2'bxx, got %b", result);
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pass = 1'b0;
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end
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result = in <<< shift;
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if (result !== 2'bxx) begin
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$display("Failed <<<, expected 2'bxx, got %b", result);
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pass = 1'b0;
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end
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result = in >> shift;
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if (result !== 2'bxx) begin
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$display("Failed >>, expected 2'bxx, got %b", result);
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pass = 1'b0;
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end
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result = in >>> shift;
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if (result !== 2'bxx) begin
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$display("Failed >>>, expected 2'bxx, got %b", result);
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pass = 1'b0;
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end
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ins = 2'b10;
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result = ins >>> shift;
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if (result !== 2'bxx) begin
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$display("Failed >>> (signed), expected 2'bxx, got %b", result);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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