38 lines
624 B
Verilog
38 lines
624 B
Verilog
module test();
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reg [13:0] a;
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reg b;
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reg c;
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always @(a or b)
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begin
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case ({1'b0,~b,a[3:0]})
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6'b00_0000 : begin
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c = 1'b1;
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end
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default : begin
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c = 1'b0;
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end
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endcase
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end
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initial begin
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#1 /* Wait for the always block above to get settled. */;
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a = 0;
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b = 0;
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#1 if (c !== 0) begin
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$display("FAILED - a=%b, b=%b, c=%b", a, b, c);
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$finish;
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end
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b = 1;
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#1 if (c !== 1) begin
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$display("FAILED - a=%b, b=%b, c=%b", a, b, c);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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