27 lines
580 B
Verilog
27 lines
580 B
Verilog
module top;
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reg pass;
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reg [31:0] in2;
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integer in1;
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reg signed [128:0] res;
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initial begin
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pass = 1'b1;
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in1 = -2; in2 = 63;
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res = in1 ** in2;
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if (res !== -128'sd9223372036854775808) begin
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$display("Failed: -2 ** 65, expected -9223372036854775808, got %0d", res);
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pass = 1'b0;
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end
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in1 = -2; in2 = 65;
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res = in1 ** in2;
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if (res !== -128'sd36893488147419103232) begin
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$display("Failed: -2 ** 65, expected -36893488147419103232, got %0d", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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