This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
iverilog
mirror of
https://github.com/steveicarus/iverilog.git
Watch
1
Star
0
Fork
You've already forked iverilog
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
bf521c7eec
iverilog
/
ivtest
/
ivltests
/
pr2248925.v
11 lines
103 B
Verilog
Raw
Blame
History
module
bug
(
)
;
time
t1
;
initial
begin
t1
=
1000
;
$display
(
"
%0d
"
,
t1
+
1000
-
500
)
;
end
endmodule
Reference in New Issue
View Git Blame
Copy Permalink