36 lines
744 B
Verilog
36 lines
744 B
Verilog
module bug05_integerRem;
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reg passed;
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reg signed[31:0] reg0;
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reg signed[31:0] reg1;
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reg signed[31:0] rrem;
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wire signed[31:0] dividend=reg0;
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wire signed[31:0] divisor=reg1;
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wire signed[31:0] remainder;
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assign remainder= dividend%divisor;
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initial begin
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passed = 1'b1;
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reg0=32'hffffffff;
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reg1=32'h0d1f0796;
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//BUG here: remainder==32'h06b26fdd, should be 32'hffffffff
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#1 if (remainder !== 32'hffffffff) begin
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$display("Failed: CA remainder, expected 32'hffffffff, got %h",
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remainder);
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passed = 1'b0;
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end
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rrem = reg0 % reg1;
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#1 if (rrem !== 32'hffffffff) begin
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$display("Failed: remainder, expected 32'hffffffff, got %h",
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rrem);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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