60 lines
1.3 KiB
Verilog
60 lines
1.3 KiB
Verilog
module top;
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reg passed;
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reg [1:0] sel;
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reg [1:0] A;
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wire Z;
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parent parent(.sel(sel), .A(A), .Z(Z));
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initial begin
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// $monitor("1: %b, 0: %b", parent.child[1].Z, parent.child[0].Z);
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passed = 1'b1;
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sel = 2'b11;
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A = 2'b00;
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#1 if (Z !== 1'b0) begin
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$display("FAILED: selected both, expected 1'b0, got %b", Z);
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passed = 1'b0;
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end
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A = 2'b11;
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#1 if (Z !== 1'b1) begin
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$display("FAILED: selected both, expected 1'b1, got %b", Z);
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passed = 1'b0;
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end
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A = 2'b10;
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#1 if (Z !== 1'bx) begin
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$display("FAILED: selected both, expected 1'bx, got %b", Z);
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passed = 1'b0;
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end
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sel = 2'b00;
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#1 if (Z !== 1'bz) begin
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$display("FAILED: deselected, expected 1'bz, got %b", Z);
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passed = 1'b0;
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end
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sel = 2'b10;
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#1 if (Z !== 1'b1) begin
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$display("FAILED: selected (1), expected 1'b1, got %b", Z);
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passed = 1'b0;
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end
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sel = 2'b01;
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#1 if (Z !== 1'b0) begin
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$display("FAILED: selected (0), expected 1'b0, got %b", Z);
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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module parent(input[1:0] sel, input [1:0] A, inout Z);
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child child[1:0](.sel(sel), .A(A), .Z(Z));
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endmodule
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module child(input sel, input A, inout Z);
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assign Z = (sel) ? A : 1'bz;
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endmodule
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