22 lines
458 B
Verilog
22 lines
458 B
Verilog
module top;
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reg passed;
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initial begin
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passed = 1'b1;
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if ($test$plusargs("opt") == 0) begin
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$display("Failed to find +opt");
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passed = 1'b0;
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end
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if ($test$plusargs("option") == 0) begin
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$display("Failed to find +option");
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passed = 1'b0;
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end
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if ($test$plusargs("options") != 0) begin
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$display("Failed, found +options");
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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