20 lines
621 B
Verilog
20 lines
621 B
Verilog
/*
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* This is a reduced example from comp1001 to demonstrate a problem
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* in Icarus Verilog. Since this fails using just the compiler this
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* appears to be a problem in the elaboration of the expression.
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*
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* The division should be done at the L-value width not at the
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* argument width. This is not the case for this example.
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*/
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module compl1001;
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reg [133:124]r66;
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initial begin
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// r66 = ((!1'b1) / ((18'h0 - (1'b1 + 1'b1)) <= 10'h000));
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r66 = (!1'b1) / 1'b0; // This fails.
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// r66 = 1'b0 / 1'b0; // This passes.
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if (r66 !== 10'bx) $display("FAILED");
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else $display("PASSED");
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end
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endmodule
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