33 lines
398 B
Verilog
33 lines
398 B
Verilog
module t();
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parameter eh = 11;
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parameter mh = 52;
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parameter ih2 = 6;
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parameter fh = 7;
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localparam ih = 1 << ih2;
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reg [ih - 1:0] i_abs;
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reg at;
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reg [ih2 - 1:0] fls;
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wire [ih - 1:0] i_norm;
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assign i_norm = i_abs << (at ? ih - mh - 1 : fls);
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initial
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begin
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at = 1;
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fls = 123;
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i_abs = 'h123;
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#1;
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if(i_norm !== ('h123 << 11))
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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