25 lines
501 B
Verilog
25 lines
501 B
Verilog
module top;
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tb #(1024) dut();
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defparam dut.Y = 2048;
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endmodule
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module tb;
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reg pass = 1'b1;
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parameter Z = 256;
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parameter Y = 128;
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parameter B = $clog2(Z);
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localparam C = $clog2(Y);
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initial begin
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if (B !== 10) begin
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$display("FAILED: parameter value, expected 10, got %0d", B);
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pass = 1'b0;
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end
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if (C !== 11) begin
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$display("FAILED: localparam value, expected 11, got %0d", C);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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