31 lines
602 B
Verilog
31 lines
602 B
Verilog
module signed_mux_bug();
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reg s;
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reg [3:0] a, b;
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reg [7:0] y, z;
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initial begin
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// Example vector
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s = 1'b1;
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a = 4'b1010;
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b = 4'b0000;
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// Manually sign extend operands before multiplexer
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y = s ? {{4{a[3]}}, a} : {{4{b[3]}}, b};
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// Use $signed() to sign extend operands before multiplexer
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// - Note that Icarus is not sign extending as expected
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z = s ? $signed(a) : $signed(b);
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// Display results
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$display("a = %b", a);
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$display("b = %b", b);
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$display("y = %b", y);
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$display("z = %b", z);
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// Finished
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$finish(0);
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end
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endmodule
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