26 lines
319 B
Verilog
26 lines
319 B
Verilog
module pr2132552();
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task test_task;
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parameter depth = 16;
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parameter width = 8;
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reg [width-1:0] mem [depth-1:0];
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integer i;
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begin
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for (i = 0; i < depth; i = i + 1) begin
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mem[i] = i;
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end
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for (i = 0; i < depth; i = i + 1) begin
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$display("%0d", mem[i]);
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end
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end
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endtask
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initial test_task;
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endmodule
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