22 lines
620 B
Verilog
22 lines
620 B
Verilog
/*
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* Based on Request id 2091455 in the iverilog Bugs database
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*/
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module main;
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parameter foo = 2;
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generate
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case (foo)
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0: initial #1 $display("I am in %m, case foo=%0d", foo);
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1: initial #1 $display("I am in %m, case foo=%0d", foo);
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2: initial #1 $display("I am in %m, case foo=%0d", foo);
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endcase // case (foo)
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case (foo)
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0: begin : X initial $display("I am in %m, case foo=%0d", foo); end
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1: begin : X initial $display("I am in %m, case foo=%0d", foo); end
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2: begin : X initial $display("I am in %m, case foo=%0d", foo); end
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endcase // case (foo)
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endgenerate
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endmodule // bug
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