39 lines
573 B
Verilog
39 lines
573 B
Verilog
// Copyright 2008, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module array_port_events();
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reg [1:0] Data[3:0];
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reg [1:0] Index;
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reg [1:0] Value;
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integer i;
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integer j;
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initial begin
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for (i = 0; i < 4; i = i + 1) begin
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Index = i;
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for (j = 0; j < 4; j = j + 1) begin
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Data[i] = i + j;
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#2;
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end
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end
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end
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always @* begin
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case (Index)
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0 : Value = Data[0];
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1 : Value = Data[1];
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2 : Value = Data[2];
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3 : Value = Data[3];
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endcase
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end
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always @(Value) begin
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#1 $display("%d", Value);
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end
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endmodule
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