73 lines
1.2 KiB
Verilog
73 lines
1.2 KiB
Verilog
module top;
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reg pass = 1'b1;
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reg result;
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function freg;
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input reg in;
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freg = in;
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endfunction
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function fnreg(input reg in);
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fnreg = in;
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endfunction
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task toreg;
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output reg out;
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input reg in;
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out = in;
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endtask
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task tnoreg(output reg out, input reg in);
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out = in;
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endtask
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task tioreg;
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inout reg io;
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io = 1'b1;
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endtask
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task tnioreg(inout reg io);
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io = 1'b0;
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endtask
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initial begin
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result = freg(1'b1);
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if (result !== 1'b1) begin
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$display("FAILED: freg()");
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pass = 1'b0;
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end
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result = fnreg(1'b0);
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if (result !== 1'b0) begin
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$display("FAILED: fnreg()");
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pass = 1'b0;
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end
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toreg(result, 1'b1);
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if (result !== 1'b1) begin
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$display("FAILED: toreg()");
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pass = 1'b0;
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end
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tnoreg(result, 1'b0);
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if (result !== 1'b0) begin
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$display("FAILED: tnoreg()");
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pass = 1'b0;
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end
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tioreg(result);
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if (result !== 1'b1) begin
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$display("FAILED: tioreg()");
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pass = 1'b0;
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end
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tnioreg(result);
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if (result !== 1'b0) begin
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$display("FAILED: tnioreg()");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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