40 lines
684 B
Verilog
40 lines
684 B
Verilog
module top;
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reg clk;
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reg pass = 1'b1;
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generate
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genvar n;
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for (n=0; n<4; n=n+1) begin : loop
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reg [n:0] r;
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always @(clk) r = n;
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end
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endgenerate
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initial begin
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clk = 0;
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#1;
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if (loop[0].r !== 0) begin
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$display("Failed generate instance 0");
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pass = 1'b0;
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end
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if (loop[1].r !== 1) begin
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$display("Failed generate instance 1");
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pass = 1'b0;
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end
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if (loop[2].r !== 2) begin
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$display("Failed generate instance 2");
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pass = 1'b0;
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end
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if (loop[3].r !== 3) begin
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$display("Failed generate instance 3");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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