38 lines
549 B
Verilog
38 lines
549 B
Verilog
// $ iverilog -Wall simpler.v -o simpler
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// $ vvp simpler
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// simpler:37: syntax error
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`timescale 1ns / 1ns
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module simpler;
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reg [1:0] cnt=0;
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wire result;
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defparam \Mcount_cnt_xor<3>11 .INIT = 4'hC;
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test_lut \Mcount_cnt_xor<3>11 (
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.a0(cnt[0]),
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.a1(cnt[1]),
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.O(result)
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);
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initial $display("PASSED");
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endmodule
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module test_lut (output O, input a0, input a1);
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parameter INIT = 4'h0;
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reg tmp;
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always @(*) tmp = mux ( INIT, {a1, a0});
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assign O = tmp;
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function mux;
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input [3:0] d;
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input [1:0] s;
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mux = d[s];
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endfunction
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endmodule
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