40 lines
737 B
Verilog
40 lines
737 B
Verilog
module test;
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reg pass = 1'b1;
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reg array[1:0];
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reg [7:0] delay[1:0];
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integer i = 1, j = 0;
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initial begin
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delay[0] = 8'd4;
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delay[1] = 8'd6;
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array[j] <= #(delay[0]) 1'b0;
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array[i] <= #(delay[i]) 1'b1;
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#3;
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if (array[0] !== 1'bx) begin
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$display("FAILED: array[0] != 1'bx @ 3");
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pass = 1'b0;
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end
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#2;
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if (array[0] !== 1'b0) begin
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$display("FAILED: array[0] != 1'b0 @ 5");
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pass = 1'b0;
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end
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if (array[1] !== 1'bx) begin
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$display("FAILED: array[1] != 1'bx @ 5");
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pass = 1'b0;
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end
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#2;
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if (array[1] !== 1'b1) begin
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$display("FAILED: array[1] != 1'b1 @ 7");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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