35 lines
677 B
Verilog
35 lines
677 B
Verilog
module top;
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reg pass = 1'b1;
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reg [7:0] d_reg = 8'b10100101;
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wire [7:0] d_wire = 8'b01011010;
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test tstr(d_reg);
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test tstw(d_wire);
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initial begin
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#1;
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/* Check with a register. */
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if (tstr.data_in_array[3] != d_reg) begin
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$display("FAILED: with a register value.");
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pass = 1'b0;
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end
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/* Check with a wire. */
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if (tstw.data_in_array[3] != d_wire) begin
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$display("FAILED: with a net value.");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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module test(input [8:1] data_in) ;
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wire [7:0] data_in_array[4:3];
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assign data_in_array[3] = data_in;
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assign data_in_array[4] = 8'b0;
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endmodule
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