29 lines
389 B
Verilog
29 lines
389 B
Verilog
`timescale 1ns/1ns
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module test();
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reg [4 : 0] A = 5'b0;
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reg CLK = 1'b0;
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parameter stages = 0;
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integer pipe;
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initial
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begin
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#2000 $display("PASSED");
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$finish;
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end
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always #20 CLK = !CLK;
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always @(posedge CLK)
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for(pipe = 2; pipe <= stages -1; pipe = pipe + 1) begin
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$display("FAILED");
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$finish;
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A<=A+1;
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end
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endmodule // test
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