38 lines
1000 B
Verilog
38 lines
1000 B
Verilog
module top;
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real rl1, rl2;
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wire eq, ne, gt, ge, lt, le;
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reg passed = 1'b1;
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// Check that a decimal constant is converted to a real value.
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assign eq = rl2 == 0;
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// assign eq = rl2 == rl1;
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assign ne = rl2 != rl1;
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assign gt = rl2 > rl1;
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assign ge = rl2 >= rl1;
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assign lt = rl2 < rl1;
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assign le = rl2 <= rl1;
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initial begin
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rl1 = 0.0;
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rl2 = 0.0;
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#1 if ({eq,ne,gt,ge,lt,le} != 6'b100101) begin
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$display("Failed: expected %b, received %b", 6'b100101,
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{eq,ne,gt,ge,lt,le});
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passed = 1'b0;
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end
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#1 rl2 = -1.0;
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#1 if ({eq,ne,gt,ge,lt,le} != 6'b010011) begin
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$display("Failed: expected %b, received %b", 6'b010011,
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{eq,ne,gt,ge,lt,le});
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passed = 1'b0;
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end
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#1 rl2 = 1.0;
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#1 if ({eq,ne,gt,ge,lt,le} != 6'b011100) begin
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$display("Failed: expected %b, received %b", 6'b001100,
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{eq,ne,gt,ge,lt,le});
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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