29 lines
629 B
Verilog
29 lines
629 B
Verilog
module top;
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parameter amax = 9;
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reg [31:0] mem [amax:0];
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integer i, tmp;
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integer fail [amax:0];
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integer pass;
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initial begin
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pass = 1;
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for (i=0; i<amax; i=i+1) begin
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fail[i] = i;
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mem[i] = i;
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end
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for (i=0; i<(amax-1); i=i+1) begin
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mem[fail[i]] = mem[fail[i]] + 1;
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// tmp = fail[i];
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// mem[tmp] = mem[tmp] + 1;
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end
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for (i=0; i<(amax-1); i=i+1) begin
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if (mem[i] != i+1) begin
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pass = 0;
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$display("Failed location %d, value was %d, expected %d",
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i, mem[i], i+1);
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end
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end
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if (pass) $display("PASSED");
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end
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endmodule
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