127 lines
2.7 KiB
Verilog
127 lines
2.7 KiB
Verilog
// Note: The for is translated to a begin/while is it tests the while.
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module main;
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reg val = 1'b0;
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reg cond = 1'b1;
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reg [1:0] cval;
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integer idx;
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integer dly = 1;
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// Simple assign (error).
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always val = 1'b1;
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// A zero delay assign (error).
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always #0 val = 1'b1;
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// A variable delay assign (warning).
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always #dly val = 1'b1;
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// Non-blocking assign (error).
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always val <= #1 1'b1;
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// No delay if (error).
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always if (cond) val = 1'b1;
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// No delay if/else (error).
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always if (cond) val = 1'b1; else val = 1'b0;
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// Delay if/no delay else (warning).
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always if (cond) #1 val = 1'b1; else val = 1'b0;
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// Delay if/no delay else (warning).
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always #0 if (cond) #1 val = 1'b1; else val = 1'b0;
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// No delay if/delay else (warning).
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always if (cond) val = 1'b1; else #1 val = 1'b0;
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// No delay forever (error).
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always forever val = 1'b1;
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// Zero delay forever (error).
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always forever #0 val = 1'b1;
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// Possible delay forever (warning).
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always forever if (cond) #1 val = 1'b1; else val = 1'b0;
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// No delay for (error).
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always for(idx=0; idx<1; idx=idx+1) val = 1'b1;
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// Zero delay for (error).
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always for(idx=0; idx<1; idx=idx+1) #0 val = 1'b1;
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// Possible delay for (warning).
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always for(idx=0; idx<1; idx=idx+1) if (cond) #1 val = 1'b1; else val = 1'b0;
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// Never run for (error).
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always for(idx=0; 0; idx=idx+1) #1 val = 1'b1;
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// Always run for (error).
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always for(idx=0; 1; idx=idx+1) #0 val = 1'b1;
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// An empty bock (error).
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always begin end
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// Block with no delay (error).
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always begin val = 1'b1; end
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// Block with zero delay (error).
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always begin #0 val = 1'b1; end
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// Block with zero delay (warning).
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always begin #0; if (cond) #1 val = 1'b1; else val = 1'b0; end
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// Never run repeat (error).
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always repeat(0) #1 val = 1'b1;
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// Always run repeat (error).
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always repeat(1) #0 val = 1'b1;
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// Possibly run repeat (warning).
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always repeat(cond) #1 val = 1'b1;
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// No wait (error).
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always wait(1) val = 1'b1;
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// May wait (warning).
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always wait(cond) val = 1'b1;
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// Not all paths covered (warning).
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always case(cval)
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2'b00: #1 val = 1'b1;
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2'b10: #1 val = 1'b1;
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endcase
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// Not all paths have delay (warning).
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always case(cval)
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2'b00: #1 val = 1'b1;
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2'b10: #1 val = 1'b1;
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default: #0 val = 1'b1;
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endcase
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// Check task calls (error, error, warning).
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always no_delay;
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always zero_delay;
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always possible_delay;
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task no_delay;
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val = 1'b1;
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endtask
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task zero_delay;
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#0 val = 1'b1;
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endtask
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task possible_delay;
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#dly val = 1'b1;
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endtask
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// Check a function call (error).
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always val = func(1'b1);
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function func;
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input in;
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func = in;
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endfunction
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endmodule
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