118 lines
2.1 KiB
Verilog
118 lines
2.1 KiB
Verilog
module main;
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reg pass = 1'b1;
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reg v1 = 1'b0;
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reg v2 = 1'b0;
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reg v3 = 1'b0;
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reg v4 = 1'b0;
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reg v5 = 1'b0;
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reg v6 = 1'b0;
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reg v7 = 1'b0;
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reg v8 = 1'b0;
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reg v9 = 1'b0;
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reg v10 = 1'b0;
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reg v11 = 1'b0;
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reg v12 = 1'b0;
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reg cond = 1'b1;
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reg [1:0] cval = 2'b00;
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always #1 v1 = 1'b1;
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always v2 = #1 1'b1;
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always if (1'b1) #1 v3 = 1'b1;
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// This will pass since the else is optimized away!
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always if (1'b1) #1 v4 = 1'b1; else v4 = 1'b0;
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always if (cond) #1 v5 = 1'b1; else #1 v5 = 1'b0;
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always begin #1 v6 = 1'b1; end // 1
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always begin #1; v7 = 1'b1; end // 2
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always begin #0; #1 v8 = 1'b1; end // 3
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always begin if (cond) #1 v9 = 1'b0; else v9 = 1'b0; #1 v9 = 1'b1; end // 4
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always repeat(1) #1 v10 = 1'b1;
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always case(cval)
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2'b00: #1 v11 = 1'b1;
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2'b01: #1 v11 = 1'bx;
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default: #1 v11 = 1'bz;
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endcase
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always definite_delay;
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task definite_delay;
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#1 v12 = 1'b1;
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endtask
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initial begin
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#3;
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if (v1 != 1'b1) begin
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$display("Failed delayed assignment.");
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pass = 1'b0;
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end
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if (v2 != 1'b1) begin
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$display("Failed intra-assignment delay.");
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pass = 1'b0;
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end
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if (v3 != 1'b1) begin
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$display("Failed simple if statement.");
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pass = 1'b0;
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end
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if (v4 != 1'b1) begin
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$display("Failed constant if/else statement.");
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pass = 1'b0;
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end
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if (v5 != 1'b1) begin
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$display("Failed if/else statement.");
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pass = 1'b0;
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end
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if (v6 != 1'b1) begin
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$display("Failed block (1).");
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pass = 1'b0;
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end
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if (v7 != 1'b1) begin
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$display("Failed block (2).");
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pass = 1'b0;
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end
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if (v8 != 1'b1) begin
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$display("Failed block (3).");
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pass = 1'b0;
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end
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if (v9 != 1'b1) begin
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$display("Failed block (4).");
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pass = 1'b0;
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end
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if (v10 != 1'b1) begin
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$display("Failed repeat.");
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pass = 1'b0;
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end
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if (v11 != 1'b1) begin
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$display("Failed case.");
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pass = 1'b0;
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end
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if (v12 != 1'b1) begin
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$display("Failed task.");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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$finish;
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end
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endmodule
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