19 lines
401 B
Verilog
19 lines
401 B
Verilog
// PR1841300
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// The output should be:
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// a is '14'; b is 'fffffff4'; c is 'fffffff4'
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module test;
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reg[4:0] a;
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reg [31:0] b, c;
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initial begin
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a = 5'b10100;
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b = $signed(a);
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c = $signed(_$Finv5(32'hab));
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$display("a is '%h'; b is '%h'; c is '%h'", a, b, c);
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end
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function [4:0] _$Finv5;
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input l;
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reg [4:0] l;
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_$Finv5 = ~l;
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endfunction
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endmodule
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